Field
Embodiments of the present disclosure generally relate to the fabrication of integrated circuits and particularly to methods for changing critical dimensions of features during an etching process.
Description of the Related Art
Reducing the size of integrated circuits (ICs) results in improved performance, increased capacity and/or reduced cost. Each size reduction requires more sophisticated techniques to form the ICs. Photolithography is commonly used to pattern ICs on a substrate. An exemplary feature of an IC is a line of a material which may be a metal, semiconductor or insulator. Line width is the width of the line and the spacing is the distance between adjacent lines. Pitch is defined as the distance between a same point on two adjacent lines. The pitch is equal to the sum of the line width and the spacing. However, due to factors such as optics and light or radiation wavelength, photolithography techniques have a minimum pitch below which a particular photolithographic technique may not reliably form features. Thus, the minimum pitch of a photolithographic technique can limit feature size reduction. Similarly, patterning tools designed to create vias or line interconnects 100 nm wide or more are not commonly able to create smaller vias. Therefore, as devices shrink to these small dimensions, current lithography processes are challenged to create patterns with the chosen critical dimensions (CD).
Variations in the width of an IC feature along one edge is typically called line-edge roughness (LER). LER has increasingly become a concern in advanced technology nodes, such as for feature sizes on the order of 100 nm or less. In one example, when considering LER below 14 nm technology node, uncontrolled LER can lead to leaky transistor failure in Front-End-Of-line (FEOL) applications, or reliability loss at the interconnect level in Back-End-Of-Line (BEOL) applications. Current LER is close to 4-5 nm for both Immersion lithography, and EUV lithography.
One approach to reduce LER is by photoresist curing using implant or e-Beam. However, these approaches decrease throughput and are not cost effective. Further, the photoresist curing methods recited above do not provide Critical Dimension (CD) shrink. CD shrink is required either to extend current Immersion lithography flow, or to help get narrower dimension with EUV.
Given the current state of the art, there is a continuing need for reduced CD and LER reduction for advanced technology node applications.